A voltage controlled oscillator (VCO) is an important building block, which is used in phase-locked loops, clock recovery circuits and frequency synthesizers. High frequency and radio frequency (RF) voltage/current controlled oscillators can be implemented monolithically as inductive-capacitive (LC) oscillators, relaxation oscillators and ring oscillators. Although ring oscillators tend to have poor phase noise characteristics as compared to high Q LC oscillators, they have the advantage of a wider range of oscillation and ease of monolithic integration which results in desirable small integrated circuit die size. Ring oscillators are particularly attractive for use in quadrature clocks and multiphase clock signal generation which is required for many clock recovery circuits and high-speed sampling systems.
High frequency of operation is an important property of many data communication transceivers, wherein the maximum VCO oscillating frequency often limits the maximum obtainable data rate. The oscillation frequency of a conventional ring oscillator is determined by the gate delay in inverting stages and the number of gates in the oscillator. The maximum frequency is attained with an oscillator consisting in three inverters, as described in U.S. Pat. No. 5,457,429 issued Oct. 10, 1995, invented by A. Ogawa et al, and in U.S. Pat. No. 5,677,650 issued Oct. 14, 1997, invented by T. Kwasniewski et al.
In order to obtain additional output oscillation phases which have fixed phase delay with respect to each other, additional gates must be added to the loop. However, the addition of gates reduces the maximum obtainable oscillation frequency. Although a negatively skewed delay scheme had been proposed to reduce the cell delay by S. J. Lee et al in the publication "A Novel High-Speed Ring Oscillator For Multiphase Clock Generation Using Negative Skewed Delay Scheme", in IEEE J. Solid State Circuits, vol. 32, pp. 289-291, February 1997, it has been found that the circuit is sensitive to power supply noise, since the conventional single-ended CMOS inverters which are used have a gate-source voltage which is proportional to the power-supply voltage. When the power supply voltage increases, the charging and discharging currents of the inverters increase in proportion to the square of the power-supply voltage. When the skew delay is larger than twice the inverter delay, the overlap period for both NMOS and PMOS conduction is so high as to cause an undesireably large increase in power consumption.